Semiconductor memory device including a field effect transistor

ABSTRACT

A semiconductor memory device including a field effect transistor associated with a semiconductor substrate and a capacitor. The capacitor is connected to a drain region of the transistor. Specifically, the capacitor includes a dielectric layer including a ferroelectric material. The capacitor is located above a gate electrode of the transistor and completely overlaps the gate electrode. The device may also include a pair of field effect transistors wherein each source of the transistors shares a common impurity doped region of the semiconductor substrate.

This is a Divisional application of Ser. No. 08/250,344, filed May 27, 1994 now U.S. Pat. No. 5,665,210; which itself is a continuation of Ser. No. 08/041,520, filed Mar. 30, 1993, now abandoned; which itself is continuation of Ser. No. 07/729,533, filed Jul. 15, 1991, now abandoned.

BACKGROUND OF THE INVENTION

The present invention relates to a method of forming insulating films in general. More particularly, it relates to such a method of sputtering suitable for forming excellent dielectric films suitable for use in capacitances.

In the recent years, dielectric (insulating) films deposited by CVD have been utilized to form capacitances for use in integrated semiconductor devices. The employment of CVD makes it possible to deposit dielectric films at low temperatures up to 450° C. so that inexpensive substrates such as soda lime glass or borosilicate glass substrates can be used. Similar low temperature deposition can be accomplished also by plasma CVD and sputtering in an atmosphere comprising an inert gas such as argon at a density of 100% to 80%. The use of argon has been known to increase the sputtering yield.

In accordance with experiments of the inventor, it has been found that the number of the interface states occurring between the dielectric film and the underlying electrical active region seriously depends upon the argon density of the sputtering atmosphere. A conspicuous example is the case of dielectric films made of tantalum oxide. In this case, many clusters of tantalum atoms of 5 to 50 Å diameter are formed in the oxide film due to stability of metal tantalum. It has been also found that the argon density significantly influences the difference in flat band voltage from the ideal value which indicates the degradation of the film and reflects the state number of fixed charge and the clusters.

There are other attempts to form dielectric films by the use of photo-CVD. In this case, the underlying surface is less damaged and the density of interface states is as low as 2×10¹⁰ eV⁻¹ cm⁻². On the other hand, the deposition of photo-CVD takes much time to complete due to very slow deposition speed so as not to be utilized for massproduction. Furthermore, the long-term reliability is not sure because of hot-electron effect resulting from hydrogen utilized during deposition.

BRIEF SUMMARY OF THE INVENTION

It is an object of the present invention to provide a method of forming high quality insulating films by deposition at low temperatures suitable for use in capacitances.

It is another object of the present invention to provide a method of forming high quality insulating films having high reliability.

It is a further object of the present invention to provide a method of forming a semiconductor device having high reliability.

Additional objects, advantages and novel features of the present invention will be set forth in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the present invention. The object and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

To achieve the foregoing and other object, and in accordance with the present invention, as embodied and broadly described herein, a dielectric material or an insulating material is sputtered on a substrate in a particularly appropriate atmosphere. Unlike conventional process, the atmosphere is characterized in that no or small proportion of an inert gas, typically argon, is utilized. The inventors have presumed that the disadvantages of argon atoms include stoichiometric disturbance in the product of sputtering and damage or defects caused by collision of argon ions or argon atoms with the dielectric film resulting in formation of fixed charge.

In the case of sputtering of a metal oxide such as tantalum oxide, titanium oxide or other suitable oxide dielectric materials and barium titanate, lead titanate or similar ferroelectric materials, the inside of a sputtering apparatus is filled with an oxidizing gas containing an inert gas at 25 vol. % or less, e.g. a mixture of oxygen (100% to 75% in volume) and argon (0% to 25% in volume). Other suitable oxidizing gases include N₂ O and O₃. Particularly, in the case of O₂ or O₃, unnecessary atoms are not introduced into the oxide film resulting in few pinholes, little damage to dielectric properties and decreased dispersion in dielectric strength. O₃ tends to be decomposed to yield oxygen radicals which enhance progress of the deposition. Usually, a bulk of a desired one of these oxides is used as the target of the sputtering. A simple metal such as tantalum can be also used as the target by suitably selecting the sputtering condition as explained in the following detailed description.

In the case of sputtering of nitrides, e.g. insulating nitrides such as silicon nitride and aluminum nitride, or resistive nitrides such as tantalum nitride, titanium nitride or other suitable nitride, the inside of a sputtering apparatus is filled with a nitride compound gas containing an inert gas at 50 vol. % or less, preferably 25 vol. % or less, e.g. a mixture of nitrogen (100 vol. % to 75 vol. %) and argon (0 vol. % to 25 vol. %). Other suitable nitride compound gases include ammonia (NH₃). Particularly, when very pure nitrogen such as vaporized from liquid nitrogen is used, unnecessary atoms are not introduced into the nitride film resulting in few pinholes, little damage to dielectric property and small dispersion in dielectric strength.

The quality of insulating films can be furthermore improved by using a halogen which would terminate dangling bonds and neutralize alkali ions inadvertently introduced into the films. In this case, a halogen compound gas is introduced together with the process gas into the sputtering apparatus at 0.2 to 20 vol %. The halogen compound gases include fluorine compounds such as NF₃, N₂ F₄, HF, chloro-fluoro carbon and F₂ and chlorine compounds such as CCl₄, Cl₂ and HCl. If the halogen is introduced too much, the content of the insulating film might be altered. The concentration of the halogen are limited to 0.01 to 5 atom % in general.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and form a part of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1(A) is a side view showing a MIS (metal-insulator-semiconductor) device manufactured in accordance with a first embodiment of the present invention.

FIG. 1(B) is a graphical diagram for explaining the displacement of the flat band voltage.

FIG. 2 is a graphical diagram showing the displacement of the flat band voltage versus the argon proportion to an argon and O₂ mixture in the sputtering atmosphere.

FIGS. 3(A) and 3(B) are side views showing a capacitance manufactured in accordance with a second embodiment of the present invention.

FIG. 4 is a graphical diagram showing the dielectric strength versus the argon proportion in the sputtering atmosphere.

FIG. 5 is a graphical diagram showing the relative dielectric constant versus the argon proportion in the sputtering atmosphere.

FIG. 6 is a cross sectional view showing a DRAM provided with a capacitance manufactured in accordance with the first or second embodiment of the present invention.

FIG. 7 is a cross sectional view showing another example of DRAM provided with a capacitance manufactured in accordance with the first or second embodiment of the present invention.

FIG. 8 is a graphical diagram showing the displacement of the flat band voltage versus the argon proportion to an argon and N₂ mixture in the sputtering atmosphere.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to FIGS. 1(A) and 1(B) and FIG. 2, a method of manufacturing an insulating film in accordance with a first embodiment of the present invention will be explained. A substrate 1 made of a single crystalline silicon semiconductor is disposed on a substrate holder in an RF magnetron sputtering apparatus (not shown) in which a target of Ta₂ O₅ has been mounted on a target holder in advance. After evacuating the inside of the apparatus, a gas is introduced thereinto in order to prepare a suitable atmosphere for gas discharge. The gas comprises argon and an oxidizing gaseous compound such as oxygen. Desirably, the constituent gases have 99.999% or higher purities. A tantalum oxide film 3 (insulating film) is then sputtered on the substrate 1 by causing gas discharge between the target holder and the substrate holder. After completion of deposition, the substrate 1 is removed from the apparatus and coated with a round aluminum electrode 4 having a 1 mm diameter by electron beam evaporation.

The characteristics of such insulating film in the MIS structure (Al--Ta₂ O₅ --Si) can be evaluated by displacement ΔV_(FB) of the flat band voltage through measuring the flat band voltage. For the measurement of the displacement, the insulating film is given BT (bias-temperature) treatment with a negative bias voltage of 2×10⁶ V/cm at 150° C. for 30 minutes followed by measuring the flat band voltage V_(FB1), and thereafter BT treatment with a positive bias voltage of 2×10⁶ V/cm at 150° C. for 30 minutes followed by measuring the flat band voltage V_(FB2) again. The displacement ΔV_(FB) is |V_(FB1) -V_(FB2) | as illustrated in FIG. 1(B).

The above procedure of deposition was repeated by changing the proportion of argon to oxygen from 100% to 0% for reference. The displacements ΔV_(FB) measured are plotted on a graphical diagram shown in FIG. 2. As shown in the diagram, the displacements ΔV_(FB) significantly decreased below 5 V when the argon proportion was decreased to 25% or lower. When argon was not used, i.e. pure oxygen (100%) was used, the displacements ΔV_(FB) was only 0.5 V or lower. Contrary to this, when pure argon (100%) was used, the displacements ΔV_(FB) was increased to 10 V. The displacements ΔV_(FB) was furthermore abruptly decreased to several tenths thereof by utilizing an additive of a halogen. The introduction of a halogen is carried out by introducing into the sputtering apparatus, together with oxygen, a halogen compound gas such as a nitrogen fluoride (NF₃, N₂ F₄) at 0.2 to 20 vol %. Particularly, NF₃ is most preferred because NF₃ can be handled with a little care and decomposed by small energy.

Referring next to FIG. 3, a method of manufacturing an insulating film in accordance with a second embodiment of the present invention will be explained. A substrate 1 comprising a sodalime glass plate and a SiO₂ blocking film formed thereon is disposed in a sputtering apparatus in which a target of metal tantalum has been set up in advance. After evacuating the inside of the apparatus, a gas is introduced thereinto for gas discharge. The gas comprises argon. A tantalum film 2 in the form of an island (lower electrode) is sputtered on the substrate to a thickness of 2000 Å on the substrate 1 with the aid of a metallic mask by causing gas discharge between the target holder and the substrate holder. Alternatively, a known photolithography may be utilized instead of the use of the metallic mask. The substrate temperature is 350° C. The pressure of the gas is maintained at 0.06 Torr during deposition. The input Rf energy is 100 W at 13.56 MHz.

After completion of deposition of the lower electrode 2, the gas is replaced by a mixture of oxygen (100 vol % to 0 vol %) and argon (0 vol % to 100 vol %). The Ta target is also replaced by a Ta₂ O₅ target having a 99.99% or higher purity. A tantalum oxide film 3 (insulating film) is then deposited on the lower electrode 2 by sputtering associated with gas discharge between the target holder and the substrate holder. The substrate temperature is 100° C. The pressure of the gas is maintained at 0.05 Torr during deposition. The input Rf energy is 500 W at 13.56 MHz. The distance between the substrate 1 and the target is adjusted to be 150 mm. After completion of deposition, the substrate 1 is removed from the apparatus and coated with around aluminum film 4 (upper electrode) having a 1 mm diameter by electron beam evaporation in order to form a capacitance comprising the lower and upper electrodes 2 and 4 and the interposed insulating (dielectric) film 3.

The characteristics of such a capacitance were also evaluated by measuring the displacement ΔV_(FB) of the flat band voltage. When 100% oxygen was used, a very excellent capacitance was formed. Even if argon was used up to 25%, capacitances having equivalent qualities were formed by setting the distance between the substrate 1 and the target to be larger than the appropriate value for the case of deposition using pure oxygen. Accordingly, excellent capacitances can be formed by utilizing a mixture of oxygen (100 vol % to 25 vol %) and argon (0 vol % to 75 vol %). The quality of such insulating films can be furthermore improved by introducing a halogen in the same manner as explained in conjunction with the first embodiment. In this case, the introduced halogen atoms can be activated by flash annealing using excimer laser pulses so that dangling bonds occurring in the film are neutralized by the halogen atoms and the origin of fixed charge in the film is eliminated.

FIG. 4 is a graphical diagram showing the relationship between the dielectric strength of the film 3 and the oxygen proportion to the argon-oxygen mixture. The dielectric strength is measured as the threshold voltage when the current leakage exceeds 1 μA. In this diagram, the length of vertical lines corresponds to double the standard deviations σ(X) and given center dots indicative of averages respectively. As shown in the diagram, the σ(X) decreased and the average dielectric strengths increased as the proportion increased beyond 75%. FIG. 5 is a graphical diagram showing the relationship between the relative dielectric constant of the film 3 and the oxygen proportion to the argon-oxygen mixture in the same manner. In this diagram, it is also understood that high proportions of oxygen are advantageous resulting in small dispersions.

Referring next to FIG. 6, a suitable application of the insulating film formed in accordance with the first or second embodiment of the present invention will be explained. The insulating film is used to form storage capacitances coupled with gate insulated field effect transistors for constructing a DRAM (dynamic random access memory) of 1 Tr/Cell type.

A storage element of the DRAM is of a stacked type as illustrated in FIG. 6 and comprises an n-type silicon semiconductor substrate within which a source and drain regions 8 and 9 of p-type are formed in order to define a channel region therebetween, a field insulating film 5 (LOCOS) for insulating the element from adjacent elements, a gate electrode 7 formed on the channel region through a gate insulating film 6 formed by thermal oxidation or sputtering of silicon oxide in 100% oxygen, an interlayer insulation film 14, a lower electrode 10 made of a silicon semiconductor heavily doped with phosphorus, a dielectric (insulating) film 11 and an upper electrode 12 formed of an aluminum film or a dual film comprising an aluminum layer and a tantalum layer.

The lower electrode 10 may be formed of metal tantalum, tungsten, titanium, molybdenum or any of silicides of such metals and makes electric contact with the drain region 9 through an opening formed in the interlayer film 14. The dielectric film 11 is formed of a Ta₂ O₅ film deposited by sputtering to a thickness of 300 Å to 3000 Å, typically 500 Å to 1500 Å, e.g. 1000 Å in accordance with the first or second embodiment as described above. The gate insulating film 6 can be made also from Ta₂ O₅ in place of silicon oxide. In that case, the number of interface states is as small as 2×10¹⁰ cm⁻². A storage capacitance is formed of the upper and lower electrodes 10 and 12 and the dielectric film 11 located therebetween. The formation of trapping centers of hot carriers can be avoided by forming these electrodes 10 and 12 and the dielectric film 11 in an atmosphere which has been deprived of hydrogen, which otherwise could reach to the gate insulating film by drifting (diffusion). The channel length of the element is selected between 0.1 μm and 1.0 μm, e.g. 0.5 μm so that one storage element can be formed within an area of 20 μm square. The source region 8 is connected to a bit line for example, and in that case the gate electrode 7 is connected to an address line of the memory. Such miniaturized structure becomes possible due to the large storage capacitance originating from the large relative dielectric constant (=27) of the tantalum oxide film as compared to the relative dielectric constant (=3.8) of silicon oxide. The large relative dielectric constant makes it possible to increase the thickness of the dielectric film to, e.g. 1000 Å so that electric insulation is improved and the number of pinholes is decreased. The frequency property of the tantalum oxide film is also excellent and maintained even at high frequencies. In the figure, numeral 12' designates an extension of the upper electrode of an adjacent storage element. Numeral 13 is the bit line of an adjacent element.

Referring next to FIG. 7, another application of the insulating film formed in accordance with the first or second embodiment of the present invention will be explained. The insulating film is used to form storage capacitances for a DRAM (dynamic random access memory) of 1 transistor per cell type.

A storage unit element of the DRAM illustrated in FIG. 7 can store information of two bits. The element comprises a p-type silicon semiconductor substrate within which a pair of channel regions 15 and 15' of n-type and a pair of drain regions 8 and 8' of p-type are formed, a plateau of a p-type semiconductor material forming a source region 9 located between the channel regions 15 and 15', a source electrode 19 formed on the plateau, a pair of gate electrodes 7 and 7' formed on the channel regions 15 and 15' through a gate insulating film 6 and flanking the side surface of the source region 9, a field insulating film 5 (LOCOS) for insulating the element from adjacent elements, an interlayer insulation film 14, a pair of lower electrodes 10 and 10' made of silicon semiconductor heavily doped with phosphorus, a dielectric (insulating) film 11 and a pair of upper electrodes 12 and 12' formed of an aluminum film or a dual film comprising an aluminum layer and a tantalum layer. The channel regions 15 and 15' are formed by ion implantation of boron with a mask of the plateau 9 and 19 and the field insulating film 5 to a density of 1×10¹⁵ cm⁻³ to 5×10¹⁶ cm⁻³, in advance of the formation of the gate electrodes 7 and 7', followed by ion implantation of phosphorus into the regions 8 and 8' with a mask of the plateau 9 and 19, the field insulating film 5 and the gate electrodes 7 and 7' to a density of 1×10¹⁹ cm⁻³ to 1×10²¹ cm⁻³.

The lower electrodes 10 and 10' make electric contact with the drain regions 8' and 8 through openings formed in the interlayer film 14 respectively. The dielectric film 11 is formed of a Ta₂ O₅ film deposited by sputtering to a thickness of 300 Å to 3000 Å, typically 500 Å to 1500 Å, e.g. 1000 Å in accordance with the first or second embodiment as described above in the same manner as that of the previous application. The lower electrode may be formed of metal tantalum, tungsten, titanium, molybdenum or any of silicides of these metals in place of the doped silicon semiconductor. A pair of storage capacitances 21 and 21' are formed from the upper and lower electrodes 10, 10' and 12, 12' and the dielectric film 11 therebetween. The channel length of the element is selected between 0.1 μm and 1.0 μm, e.g. 0.5 μm so that a two bit storage element can be formed within an area of 10 to 20 μm square.

Next, a method of manufacturing an insulating film in accordance with a third embodiment of the present invention will be explained. FIG. 1(A) is used again for this purpose. A substrate 1 made of a single crystalline silicon semiconductor is disposed on a substrate holder in an RF magnetron sputtering apparatus (not shown) in which a target of Si₃ N₄ has been mounted on a target holder in advance. Alternatively, the target may be made of other nitrides such as aluminum nitride, tantalum nitride, titanium nitride instead of the Si₃ N₄ target. After evacuating the inside of the apparatus, a gas is introduced thereinto in order to prepare a suitable atmosphere for gas discharge. The gas comprises argon and a nitrogen compound gas such as nitrogen. Desirably, the constituent gases have 99.9% or higher purities. The substrate temperature is 200° C. The pressure of the gas is maintained at 0.05 Torr during deposition. The input Rf energy is 500 W at 13.56 MHz. The distance between the substrate 1 and the target is adjusted to be 150 mm. A silicon nitride film 3 (insulating film) is then sputtered on the substrate 1 by causing gas discharge between the target holder and the substrate holder. After completion of deposition, the substrate 1 is removed from the apparatus and coated with a round aluminum electrode 4 having a 1 mm diameter by electron beam evaporation.

The characteristics of such insulating film in the MIS structure (Al--Si₃ N₄ --Si) can be evaluated by displacement ΔV_(FB) of the flat band voltage through measuring the flat band voltage. For the measurement of the displacement, the insulating film is given BT (bias-temperature) treatment with a negative bias voltage of 2×10⁶ V/cm at 150° C. for 30 minutes followed by measuring the flat band voltage, and thereafter BT treatment with a positive bias voltage of 2×10⁶ V/cm at 150° C. for 30 minutes followed by measuring the flat band voltage again in the same manner as for oxide films.

The above procedure of deposition was repeated by changing the proportion of argon to nitrogen from 100% to 0% for reference. The displacements ΔV_(FB) measured are plotted on a graphical diagram shown in FIG. 8. As shown in the diagram, the displacements ΔV_(FB) significantly decreased below 2 V when the argon proportion was decreased to 25% or lower. Numeral 31 designates a displacement of 11.5 V in the case of a silicon nitride film deposited by a conventional plasma CVD for reference. When argon was not used, i.e. pure nitrogen (100%) was used, the displacements ΔV_(FB) was only 0.5 V or lower as depicted by numeral 34. Contrary to this, when pure argon (100%) was used, the displacements ΔV_(FB) was increased to 13 V. The displacements ΔV_(FB) was furthermore abruptly decreased to several tenths thereof by utilizing an additive of a halogen. The introduction of a halogen is carried out by introducing into the sputtering apparatus, together with nitrogen, a halogen compound gas such as a nitrogen fluoride (NF₃, N₂ F₄) at 0.2 to 20 vol %. In this case, the introduced halogen atoms can be activated by flash annealing using excimer laser pulses so that dangling bonds occurring in the film are neutralized by the halogen atoms and the origin of fixed charge in the film is eliminated.

Referring again to FIGS. 6 and 7, suitable applications of the insulating film formed in accordance with the third embodiment of the present invention will be explained. The insulating film is used also in this case to form storage capacitances for DRAMs (dynamic random access memory) of 1 Tr/Cell type. The explanation is substantially same as given to the above applications utilizing the tantalum oxide insulating films except for the following description.

The dielectric film 11 as illustrated in FIGS. 6 and 7 is formed of a Si₃ N₄ film in this case deposited by sputtering to a thickness of 300 Å to 3000 Å, typically 500 Å to 1500 Å, e.g. 1000 Å in accordance with the third embodiment as described above. The gate insulating film 6 can be made also from Si₃ N₄ in place of silicon oxide. In that case, the number of interface states is as small as 3×10¹⁰ cm⁻². The dimension of the unit elements can be decreased in the same manner as in the applications utilizing the tantalum oxide films due to the large storage capacitance originating from the large relative dielectric constant (=6) of the silicon nitride film as compared to the relative dielectric constant (=3.8) of silicon oxide.

The foregoing description of preferred embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form described, and obviously many modifications and variations are possible in light of the above teaching. The embodiment was chosen in order to explain most clearly the principles of the invention and its practical application thereby to enable others in the art to utilize most effectively the invention in various embodiments and with various modifications as are suited to the particular use contemplated.

Although the dielectric films are deposited by RF magnetron sputtering in the above preferred embodiments, other suitable sputtering can be utilized, e.g. various known types of DC or RF sputtering methods. It is partly because of the high resistance of the targets utilized that RF magnetron sputtering is preferred. Pure metals such as tantalum and titanium, however, may be used in suitable sputtering conditions. In the case of deposition of oxide films by the use of such targets of pure metals, the atmosphere is purified to a 99.999% or higher purity and comprises 100% to 90% oxygen in which deposition of the oxide films is carried out with a lower acceleration voltage at a lower deposition speed of the order of 1/4 of the above embodiments.

The application of the present invention is not limited to the above examples but applicable for integrated circuits utilizing the capacitors of the present invention, transistors of inversed-stagger type, vertical channel transistors, other types of insulated gate field effect transistors formed within a single crystalline silicon semiconductor substrate and so forth. The capacitances can be formed into multi-layered structure or vertical type structure in which the dielectric film is sandwiched by a pair of electrodes in a lateral direction. The capacitors of the present invention can be used for dynamic memories. 

What is claimed is:
 1. A semiconductor memory device comprising:a semiconductor substrate; a pair of field effect transistors associated with said semiconductor substrate wherein each source of said transistors shares a common impurity doped region formed in a plateau elevated from said semiconductor substrate and each gate electrode of said transistors is formed over each channel region of said transistors; a first capacitor connected to a drain of one of said transistors; a second capacitor connected to a drain of another one of said transistors, wherein said each of said first and second capacitors comprises a pair of electrodes and a dielectric layer interposed therebetween, said dielectric layer comprising a ferroelectric material, and wherein each of said first and second capacitors is located over said gate electrode of the corresponding transistor so as to completely overlap said gate electrode.
 2. A semiconductor memory device according to claim 1 wherein said ferroelectric material is selected from the group consisting of barium titanate and lead titanate.
 3. A semiconductor memory device comprising:a semiconductor substrate; a pair of field effect transistors associated with said semiconductor substrate wherein each source of said transistors shares a common impurity doped region formed in a plateau elevated from said semiconductor substrate and each gate electrode of said transistors is formed over each channel region of said transistors; a first capacitor connected to a drain of one of said transistors; a second capacitor connected to a drain of another one of said transistors, and wherein each of said first and second capacitors is located over said gate electrode of the corresponding transistor so as to completely overlap said gate electrode.
 4. A semiconductor memory device according to claim 3 wherein said each channel region of said transistors is formed in said semiconductor substrate and between said plateau and each of said drain regions.
 5. A semiconductor memory device including at least first and second insulated gate field effect transistors, said device comprising:a semiconductor substrate having a first surface and a plateau elevated from said first surface; a first impurity region formed within said plateau as a source of both said first and second transistors; a pair of second impurity regions formed within said semiconductor substrate with said plateau disposed therebetween as drains of said first and second transistors, respectively; a pair of capacitors electrically connected to said pair of second impurity regions, respectively; a pair of channel regions formed within said substrate between said plateau and said pair of second impurity regions, respectively; and a pair of gate electrodes adjacent to said channel regions, respectively, wherein each of said first and second capacitors comprises a pair of electrodes and a dielectric layer interposed therebetween, said dielectric layer comprising a ferroelectric material, and wherein each of said first and second capacitors is located over said gate electrode of the corresponding transistor so as to completely overlap said gate electrode.
 6. A semiconductor device according to claim 5 wherein each of said capacitors extends beyond the associated channel region and the associated gate electrode.
 7. A semiconductor memory device comprising:a semiconductor substrate; a pair of field effect transistors associated with said semiconductor substrate, each of which comprises source and drain regions, a channel region therebetween, and a gate electrode over the channel region wherein the source regions of the pair of field effect transistors are formed in a same impurity region in a plateau elevated from said semiconductor substrate; a first capacitor connected to a drain region of one of the drains of the pair of transistors; a second capacitor connected to the other one of the drains of the pair of transistors; wherein each of said first and second capacitor has a dielectric layer, and wherein each of said first and second capacitors is located over said gate electrode of the corresponding transistor so as to completely overlap said gate electrode.
 8. The semiconductor memory device according to claim 7 wherein said dielectric layer comprises tantalum oxide.
 9. The semiconductor memory device according to claim 7 wherein said dielectric layer comprises titanium oxide.
 10. The semiconductor memory device according to claim 7 wherein said dielectric layer comprises a material selected from the group consisting of silicon nitride, tantalum nitride and titanium nitride.
 11. The semiconductor memory device according to claim 7 wherein said dielectric layer comprises a material selected from the group consisting of tantalum oxide, titanium oxide, barium titanate and lead titanate.
 12. A semiconductor memory device including at least first and second insulated gate field effect transistors, said device comprising:a semiconductor substrate having a first surface and a plateau elevated from said first surface; a first impurity region formed within said plateau as a source of both said first and second transistors; a pair of second impurity regions formed within said semiconductor substrate with said plateau disposed therebetween as drains of said first and second transistors, respectively; a pair of capacitors electrically connected to said pair of second impurity regions, respectively; a pair of channel regions formed within said substrate between said plateau and said pair of second impurity regions, respectively; and a pair of gate electrodes adjacent to said channel regions, respectively, wherein each of said first and second capacitors comprises a pair of electrodes and a dielectric layer interposed therebetween, and wherein each of said first and second capacitors is located over said gate electrode of the corresponding transistor so as to completely overlap said gate electrode.
 13. The semiconductor memory device according to claim 12 wherein said dielectric layer comprises tantalum oxide.
 14. The semiconductor memory device according to claim 12 wherein said dielectric layer comprises titanium oxide.
 15. The semiconductor memory device according to claim 12 wherein said dielectric layer comprises a material selected from the group consisting of silicon nitride, tantalum nitride and titanium nitride.
 16. A semiconductor memory device comprising:a semiconductor substrate; a pair of field effect transistors associated with said semiconductor substrate wherein each source of said transistors shares a common impurity region formed in plateau elevated from said semiconductor substrate and each gate electrode of said transistors is formed over each channel region of said transistors; a first capacitor connected to a drain of one of said transistors; a second capacitor connected to a drain of another one of said transistors, wherein each of said first and second capacitors comprises a pair of electrodes and a tantalum oxide layer interposed therebetween, and wherein each of said first and second capacitors is located over said gate electrode of the corresponding transistor so as to completely overlap said gate electrode.
 17. A semiconductor memory device according to claim 16 wherein each channel region of said transistors is formed in said semiconductor substrate and between said plateau and each of said drain regions.
 18. A semiconductor memory device comprising:a semiconductor substrate; a pair of field effect transistors associated with said semiconductor substrate wherein each source of said transistors shares a common impurity region formed in plateau elevated from said semiconductor substrate and each gate electrode of said transistors is formed over each channel region of said transistors; a first capacitor connected to a drain region of said drain regions of said pair of transistors; a second capacitor connected to the other one of said drains of said pair of transistors; wherein each of said first and second capacitors has a dielectric layer comprising tantalum oxide, and wherein each of said first and second capacitors is located over said gate electrode of the corresponding transistor so as to completely overlap said gate electrode.
 19. A semiconductor memory device according to claim 18 wherein each channel region of said transistors is formed in said semiconductor substrate and between said plateau and each of said drain regions. 